1. Field of the Invention
The present invention relates to a silica-based film forming material, which is provided for formation of air gaps that are used as an insulating structure in semiconductor substrates or semiconductor multilayer wiring substrates, and further relates to a method for forming air gaps using such a material.
2. Related Art
In recent years, intervals of wirings that connect elements have been reduced in response to enhanced integration of semiconductor devices and improved performances of large scale integrated (LSI) circuits. It is known that parasitic capacitance is generated as intervals of wirings are thus reduced, whereby decrease in such a parasitic capacitance has been demanded. Generally, SOG (spin-on glass) materials, CVD (chemical vapor deposited) materials and the like have been employed as materials that constitute interlayer insulating films, and low dielectric constant materials such as materials containing silicon and/or carbon, and materials enabling formation of fine pores have been employed for achieving low dielectric constant in these materials. However, when these low dielectric constant materials are used, problems such as reduction in mechanical strength, and lowering of process resistance reportedly occur, and thus development of means capable of decreasing parasitic capacitance without using a low dielectric constant material has been desired.
Known techniques of lowering parasitic capacitance in addition to use of a low dielectric constant material include air gap-forming techniques by which air gaps are intentionally formed among wirings. For example, Patent Document 1 discloses a method for the production of a semiconductor device which includes the steps of: forming a plurality of wirings so as to be adjacent with each other on a first insulating film which had been formed on a semiconductor substrate, and forming a second insulating film on the first insulating film with a plasma CVD method; coating wirings on the second insulating film such that air gaps are formed among adjacent wirings; and the like.    Patent Document 1: Japanese Unexamined Patent Application, Publication No. 2008-109043